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mos integrated circuit data sheet m pd75p238 4-bit single chip microcomputer document no. ic-2596a (o.d. no. ic-8014a) date published february 1994 p printed in japan ? nec corporation 1992 the information in this document is subject to change without notice. the mark h shows major revised points. description the m pd75p238 is a version of the m pd75238 in which the on-chip mask rom is replaced by one-time prom or eprom. the one-time prom version can be written to once only, and is useful for short-run and multiple device- production of sets and early start-up. also, the eprom version allows programs to be written and rewritten, and is thus ideal for system evaluation. functions are described in detail in the following user's manual, which should be read when carrying out design work. m pd75238 user's manual : ieu-731 the m pd75p238 eprom product does not provide a level of reliability suitable for use as a volume production product for users' devices. the eprom product should be used solely for function evaluation in experiments of preproduction. features o m pd75238 pin compatible o on-chip prom: 32640 8 o on-chip ram: 1024 4 o drive capability in same supply voltage range as mask version m pd75238 (2.7 to 6.0 v) o ports 4 & 5: no pull-up resistor o port 7: no pull-down resistor note no internal pull-up and pull-down resistor function by mask option. use vcr, audio-visual, ecr, microwave oven ordering information ordering code package on-chip rom quality grade m pd75p238gj-5bg 94-pin plastic qfp( n n 20 mm) one-time prom standard m pd75p238kf 94-pin ceramic wqfn eprom standard o high-voltage display outputs . s0 to s8 & t0 to t9 : internal pull-down resistors . s9, s16 to s23 & t10 to t15: open-drain please refer to quality grade on nec semiconductor devices (document number iei-1209) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. this manual describes common parts of one-time prom and eprom products as prom.
2 m pd75p238 pin configuration (top view) m pd75p238gj- 5bg m pd75p238kf 1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 12 s20/p110 s21/p111 s22/p112 s23/p113 s0/p120 92 91 90 89 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 68 66 65 64 63 62 61 60 59 58 57 55 54 53 52 51 50 48 56 24 an0 av ref av dd v dd v pp x2 x1 ic xt2 xt1 v ss s16/p100 s17/p101 s18/p102 s19/p103 p42 p43 v ss p50 p51 p52 p53 p60 p61 p62 p63 p70 p71 p72 p73 p80/ppo p81/sck1 p82/so1 p83/si1 v dd s4/p130 s5/p131 s6/p132 s7/p133 s8/p140 s9/p141 v dd v load t15/s10/p142 t14/s11/p143 ph0/t13/s12/p150 ph1/t12/s13/p151 ph2/t11/s14/p152 ph3/t10/s15/p153 t9 t8 t7 t6 t5 t4 p21 p22/pcl p23/buz p30/md0 p31/md1 an4/p90 an5/p91 an6/p92 an7/p93 av ss reset p00/int4 p01/sck0 p02/so0/sb0 p03/si0/sb1 p10 /int0 p11/int1 p12/int2 p13/ti0 p20/pto0 21 22 23 44 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 46 45 47 67 69 70 49 71 s1/p121 s2/p122 s3/p123 t3 t2 t1 t0 p41 p40 p32/md2 p33/md3 88 an3 an2 an1 93 94 remarks ic (internally connected) pins should be connected directly to v ss . note ensure that power is supplied to the v dd and v ss pins (pins 4, 11, 30, 48, and 65).
3 m pd75p238 pin name p00 to p03 : port0 sck0, sck1 : serial clock i/o 0, 1 p10 to p13 : port1 so0, so1 : serial data output 0, 1 p20 to p23 : port2 si0, si1 : serial data input 0, 1 p30 to p33 : port3 sb0, sb1 : serial bus i/o 0, 1 p40 to p43 : port4 int0, int1, int4 : external vectored interrupt input 0, 1, 4 p50 to p53 : port5 int2 : external test input 2 p60 to p63 : port6 ppo : programmable pulse output p70 to p73 : port7 ti0 : timer input 0 p80 to p83 : port8 pto0 : programmable timer output 0 p90 to p93 : port9 buz : buzzer clock p100 to p103 : port10 pcl : programmable clock output p110 to p113 : port11 an0 to an7 : analog input 0 to 7 p120 to p123 : port12 av ref : analog reference voltage p130 to p133 : port13 av dd : analog v dd p140 to p143 : port14 av ss : analog v ss p150 to p153 : port15 x1, x2 : main system clock oscillation 1, 2 ph0 to ph3 : porth xt1, xt2 : subsystem clock oscillation 1, 2 t0 to t15 : digit output reset : reset s0 to s23 : segment output v pp : programming power supply v dd : positive power supply md0 to md3 : mode selection 0 to 3 v ss : ground ic : internally connected v load : power supply for fip driver
4 m pd75p238 block diagram port 1 port 2 port 3 port 4 port 5 port 6 port 7 4 4 4 4 4 4 4 10 4 24 p00-p03 p10-p13 p20-p23 p30/md0 -p33/md3 p40-p43 p50-p53 p60-p63 p70-p73 sp (8) bank general reg. ram data memory 1024 4 decode and control cy alu program counter (15) rom program memory 32640 8 reset stand by control v dd cpu clock clock generator sub main clock divider clock output control pcl/p22 f x / 2 n basic interval timer timer/event counter #0 watch timer serial interface intw intbt intt0 sck0/p01 so0/sb0/p02 si0/sb1/p03 buz/p23 ti0/p13 pto0/p20 sbs (2) 10 8 fip controller/ driver t0-t9 t10/s15/ph3/p153- t13/s12/ph0/p150 s0/p120-s9/p141 s16/p100-s23/p113 p ort 0 4 port 8 p80-p83 4 p90-p93 4 port 9 t14/s11/ p143- t15/s10/p142 v load port 10-15 f v pp v ss timer/ pulse genelator inttpg interrupt control event counter int4/p00 int2/p12 int1/p11 int0/p10 ppo/p80 intcsi serial interface si1/p83 so1/p82 sck1/p81 a/d converter bit seq. buffer(16) an0-an3 an4/p90-an7/p93 av dd av ref av ss ti0 p100-p153 2 x2 x1 xt2 xt1 tio 8
5 m pd75p238 1. pin functions 1.1 port pins (1/2) pin name p00 p01 p02 p03 p10 p11 p12 p13 p20 p21 p22 p23 p30 to p33 *2 p40 to p43 *2 p50 to p53 *2 p60 to p63 p70 to p73 function 4-bit input port (port0). internal pull-up resistor specification by software is possible for p01 to p03 as a 3- bit unit. 4-bit input port (port1). internal pull-up resistor specification by software is possible as a 4-bit unit. 4-bit input/output port (port2). internal pull-up resistor specification by software is possible as a 4-bit unit. programmable 4-bit input/output port (port3). input/output settable bit-wise. internal pull-up resistor specification by software is possible as a 4-bit unit. n-ch open-drain 4-bit input/output port (port4). data input/output pins for program memory write/verify (low-order 4 bits). n-ch open-drain 4-bit input/output port (port5). data input/output pins for program memory write/verify (high-order 4 bits). input/output input input input/output input/output input/output input/output input/output input/output with noise elimination function dual-function pin int4 sck0 so0/sb0 si0/sb1 int0 int1 int2 ti0 pto0 pcl buz md0 to md3 *1. a circle denotes schmitt-triggerd input. 2. direct led drive capability after reset input input input input input input input input input/output circuit type *1 b f C a f C b m C c b C c e C b e C c m C a m C a e C c e 8-bit i/o programmable 4-bit input/output port (port6). input/output settable bit-wise. internal pull-up resistor specification by software is possible as a 4-bit unit. 4-bit input/output port (port7).
6 m pd75p238 1.1 port pins (2/2) dual- function pin ppo sck1 so1 si1 an4 to an7 s16 to s19 s20 to s23 s0 to s3 s4 to s7 s8 s9 s10/t15 s11/t14 s12/t13/ph0 s13/t12/ph1 s14/t11/ph2 s15/t10/ph3 s12/t13/p150 s13/t12/p151 s14/t11/p152 s15/t10/p153 input/output input/output input/output input/output input input output output output output output output function 4-bit input port (port8). 4-bit input port (port9). p-ch open-drain 4-bit high-voltage output port. p-ch open-drain 4-bit high-voltage output port. p-ch open-drain 4-bit high-voltage output port. internal pull-down resistors. p-ch open-drain 4-bit high-voltage output port. internal pull-down resistors. p-ch open-drain 4-bit high-voltage output port. internal pull-down resistor on p140 only. p-ch open-drain 4-bit high-voltage output port. p-ch open-drain 4-bit high-voltage output port. pin name p80 p81 p82 p83 p90 to p93 p100 to p103 p110 to p113 p120 to p123 p130 to p133 p140 p141 p142 *2 p143 *2 p150 *2 p151 *2 p152 *2 p153 *2 ph0 ph1 ph2 ph3 *1. a circle denotes schmitt-triggerd input. 2. direct led drive capability. 8-bit i/o after reset input input high impedance v load level v load level high impedance high impedance input/output circuit type *1 a f e b y C a i C d i C e i C e i C e i C d i C d i C d output
7 m pd75p238 1.2 non-port pins (1/2) input/output output input output output output input/output input/output input/output input input input input/output output input input input input input input input pin name ppo ti0 pto0 pcl buz sck0 so0/sb0 si0/sb1 int4 int0 int1 int2 sck1 so1 si1 an0 to an3 an4 to an7 av ref av dd av ss x1, x2 xt1 xt2 reset md0 to md3 ic v pp function timer/pulse generator pulse output pin. external event pulse input pin for timer/event counter #0 or event counter #1. timer/event counter output pin. clock output pin. fixed-frequency output pin (for buzzer or system clock trimming use). serial clock input/output pin. serial data output pin. serial bus input/output pin. serial data input pin. serial bus input/output pin. edge-detected vectored interrupt input pin (either rising or falling edge detection). edge-detected vectored interrupt input pin (detected edge selectable). edge-detection testable input pin (rising edge detection). serial clock input/output pin. serial data output pin. serial data input pin. a/d converter analog input pin. a/d converter reference voltage input pin. a/d converter power supply pin. a/d converter reference gnd potential pin. main system clock oscillation crystal/ceramic resonator input. when an external clock is used, the clock is input to x1 and the inverted clock to x2. subsystem clock oscillation crystal resonator input. when an external clock is used, the clock is input to xt1 and xt2 is left open. system reset input pin. mode selection pin for program memory write/verify. internally connected . connect to v ss directly. program voltage application pin for program memory write/verify . connected to v dd in normal operation. applies +12.5 v in program memory write/verify. clocked asynchronous asynchronous dual- function pin p80 p13 p20 p22 p23 p01 p02 p03 p00 p10 p11 p12 p81 p82 p83 p90 to p93 p30 to p33 after reset input input input input input input input input input input input/output circuit type * a b C c e C b e C b e C b f C a f C b m C c b b C c b C c f e b y y C a z b e C c * a circle denotes schmitt-triggerd input. h
8 m pd75p238 1.2 non-port pins (2/2) pin name v dd (3 pins) v ss (2 pins) v load t0 to t9 * t10/s15 to t13/s12 t14/s11 t15/s10 s0 to s3 * s4 to s7 * s8 * s9 s16 to s19 s20 to s23 input/output after reset v load level high impedance high impedance v load level v load level v load level high impedance high impedance high impedance dual- function pin ph3/p153 to ph0/p150 p143 p142 p120 to p123 p130 to p133 p140 p141 p100 to p103 p110 to p113 * internal pull-down resistor output input/output circuit type i C d i C e i C d i C d i C e i C e i C e i C d i C d i C d function positive power supply pins. apply +6 v in prom write/verify. ground potential pin. fip controller/driver pull-down resistor connection/ power supply pin. digit output high-voltage large large-current output pins. digit/segment output dual-function high-voltage large- current output pins. unused pins usable as port h. usable as port 15 in static mode. digit/segment output dual-function high-voltage large- current output pin. usable as port 14 in static mode. segment high-voltage output pins. usable as port 12 to port 14 in static mode. segment high-voltage output pins. usable as port 10 & port 11 in static mode.
9 m pd75p238 1.3 pin input/output circuits the input/output circuits for each of the pins are shown in fig. 1-1 in partially simplified form. fig. 1-1 pin input/output circuits (1/3) p-ch v dd out n-ch data output disable cmos standard input buffer push-pull output with high impedance output capability (p-ch and n-ch both off) type a type d type b type e type b-c type e-b schmitt-triggered input with hysteresis characteristics in p-ch v dd in n-ch input/output circuit composed of type d push-pull output and type a input buffer in/out data output disable type d type a in p-ch p.u.r. p.u.r. enable v dd p.u.r. : pull-up resistor p.u.r. p-ch in/out output disable data output disable type d type a p.u.r. : pull-up resistor v dd schmitt-triggered input with hysteresis characteristics
10 m pd75p238 p.u.r. p-ch in/out p.u.r. enable data output disable type d type b p.u.r. : pull-up resistor v dd in/out data output disable type d type b input /output circuit composed of type d push- pull output and type b schmitt-triggered input p.u.r. p-ch in/out p.u.r. enable data output disable type d type a p.u.r. : pull-up resistor v dd p.u.r. p-ch in/out p.u.r. enable data output disable type d type b p.u.r. : pull-up resistor v dd p-ch v dd n-ch data out p-ch v dd fig. 1-1 pin input/output circuits (2/3) type f-b type e-c type f-c type f type f-a type i-d p.u.r. in/out p.u.r. enable output disable (p-ch) output disable data output disable (n-ch) v dd v dd p-ch n-ch p-ch p.u.r. : pull-up resistor type b
11 m pd75p238 fig. 1-1 pin input/output circuits (3/3) p-ch v dd n-ch data out p-ch v dd p.d.r v load p.u.r. : pull-up resistor in/out n-ch data output disable middle-high voltage input buffer p.u.r. enable in/out p-ch v dd n-ch data output disable p.u.r. : pull-up resistor p.u.r. type b + - av dd av ss sam- pling c av dd av ss p-ch n-ch av ss in reference voltage (from series resistance string voltage tap) + - av dd av ss sam- pling c av dd av ss p-ch n-ch av ss in reference voltage (from series resistance string voltage tap) av ss type i-e type y type y-a type m-a type m-c type z p.d.r: pull-down resistor p.u.r: pull-up resistor p.u.r: pull-up resistor
12 m pd75p238 pin recommended connection p23/buz p40 to p43 p50 to p53 p60 to p63 p70 to p73 p80 to ppo p81 to sck1 p30 to p33 p22/pcl p21 p20/pto0 p13/ti0 p10/int0 to p12/int2 p03/si1/sb1 p02/so0/sb0 p00/int4 p01/sck0 p82/so1 p83/si1 p90/an4 to p93/an7 connect to v ss . connect to v ss or v dd . connect to v ss . input state : connect to v ss or v dd . output state : leave open. connect to v ss or v dd . connect to v ss . 1.4 disposition of unused pin table 1-2 recommended commection of unused pins (1/2)
13 m pd75p238 pin recommended connection table 1-2 recommended commection of unused pins (2/2) leave open. connect to v ss . connect to v dd . connect to v ss . connect to v ss or v dd . leave open. connect to v ss or leave open. p100/s16 to p103/s19 p110/s20 to p113/s23 p120 to p123 p130 to p133 p140 to p143 p150 to p153 an0 to an3 av ref av dd av ss xt1 xt2 v load ic connect to v ss . h
14 m pd75p238 2. differences between m pd75p238 and m pd75238 the m pd75p238 is a product with the program memory of the m pd75238 using on-chip mask rom replaced by one-time prom or eprom. table 2-1 shows differences between m pd75p238 and m pd75238. the differences between these products must be thoroughly checked when, for example, switching from use of prom for application system debugging and reproduction to use of a mask rom product for volume production. for details of cpu function and on-chip hardware, refer to the document " m pd75238 user's manual" (ieu-731). table 2-1 differences between m pd75p238 and m pd75238 m pd75238 parameter rom mask rom 32k 8 one-time prom, eprom 32k 8 m pd75p238 no. of segments no. of digits 1k 4 ram fip controller/ driver pull-up resistors 9 to16 9 to 24 ports 4 & 5 s0 to s8 s9 s16 to s23 t0 to t9 t10 to t15 no no on-chip no no on-chip pull-down resistors no pin 5 v dd v pp pins 70 to 73 p30/md0 to p33/md3 p30 to p33 pin connection the mask rom products and prom products have different consumption currents, operating temperature range etc. see the electrical specifications section in the relevant data sheet for details. electrical specifications 2.7 to 6.0 v operating supply voltage range subsystem clock feedback resistor mask option on-chip package 94-pin plastic qfp ( n n 20 mm) 94-pin ceramic wqfn 94-pin plastic qfp ( n n 20 mm) the mask rom products and prom products have different circuit scales and mask layouts, and therefore differ in terms of noise resistance and noise radiation. others note noise resistance and noise radiation differs between the prom products and mask rom products. when investigating a switch from preproduction to volume production, throughout evaluation should be carried out with the mask rom cs product (not the es product). port 7 mask option h h h product name
15 m pd75p238 3. program memory (prom) the program memory is prom with a 32640 8-bit configuration wich stores program and table tata etc. the program memory is addressed by the program counter. in addition, table data can be referenced by a table referencing instruction (movt). the rage of address to which branch instructions and subroutine call instructions and subroutine call instructions and subroutine call instructions can branch is shown in fig. 3-1. the entire space comprising 0000h to 7f7fh can be directly branched to by the entire-space branch instruction (bra !addr1) and the entire-space call instruction (calla !addr1). the relative branch instruction (br $ addr) allows branching to addresses [pc contents C15 to C1 and +2 to +16] irrespective of block boundaries. in addition, the following addresses are specially allocated (except for 0000h and 0001h, the entire area can be used as ordinary program memory). ? addresses 0000h & 0001h vector table to which the program start address and mbe & rbe set value upon reset input are written. reset servicing can be started from any address in the 16k (000h to 3fffh). ? addresses 0002h to 000fh vector table to which the program start address and mbe & rbe set value for the various vectore interrupts are written. interrupt servicing can be started from any address in the 16k space (0000h to 3fffh). ? addresses 0020h to 007fh table area referenced by geti instruction * . * the geti instruction allows any 2- or 3-byte instruction or any two 1-byte instructions to be implemented as 1 byte, and is used to reduce the number of program steps.
16 m pd75p238 fig. 3-1 program memory map ? ? ? mbe rbe mbe rbe mbe mbe rbe mbe rbe mbe rbe 0000h 0002h 0004h 0006h 0008h 000ah 0020h 007fh 0080h 07ffh 0fffh 7 6 0 internal reset start address (low-order 8 bits) int0 start address (high-order 6 bits) (low-order 8 bits) (low-order 8 bits) int1 start address (high-order 6 bits) (low-order 8 bits) intso start address (high-order 6 bits) (low-order 8 bits) intt0 start address (high-order 6 bits) geti instruction reference table callf ! faddr instruction entry address brcb ! caddr instruction branch address br !addr instruction branch address call !addr instruction branch address branch/call addresses by geti brcb !caddr instruction branch address ? (high-order 6 bits) rbe intbt/int4 start address (high-order 6 bits) (low-order 8 bits) mbe rbe inttpg start address (high-order 6 bits) (low-order 8 bits) 000ch mbe rbe intks start address (high-order 6 bits) (low-order 8 bits) ? ? ? ? ? ? ? ? ? ? ? ? ? ? 2000h 1fffh 2fffh 3000h 3fffh 4000h 4fffh 5000h 5fffh 6000h 6fffh 7000h 7f7fh 0800h 1000h ? brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address brcb !caddr instruction branch address bra !addr instruction branch address calla !addr instruction branch address br $addr instruction relative branch address (-15 to -1, +2 to +16) 000eh note the above interrupt vector start addresses are 14-bit, and thus should be set in the 16k space (0000h to 3fffh). remarks in addition to the above, branching is possible with the br pcde and br pcxa instructions to addresses with the low-order 8 bits only of the pc modified.
17 m pd75p238 4. stack bank selection register (sbs) the stack bank selection register specifies one memory bank from memory banks 0 to 3 as the stack area.its format is shown in fig. 4-1. the stack bank selection register is set by a 4-bit memory manipuration instruction. on reset input bit only is set to "1" and the remaining bits are undefined. therefore this register must always be initialized to 00 b * at the start of a program. fig. 4-1 stack bank selection register format 0 3 2 1 0 sbs symbol stack area specification note after reset input a subroutine call instruction and interrupt enabling instruction should be executed after setting the stack bank selection register. * should be set to the desired value. f84h sbs3 sbs2 sbs1 sbs0 address 0 0 memory bank 0 0 1 memory bank 1 1 0 memory bank 2 1 1 memory bank 3 0 ensure that 0 is written to bits 2 & 3.
18 m pd75p238 5. program memory write and verify operations the program memory incorporated in the m pd75p238 is 32640 8-bit electrically writable prom. write/verify operations on this prom are executed using the pins shown in the table below. address updating is performed by means of clock input from the x1 pin rather than by address input. table 5-1 pins used for program memory write/verify v pp x1, x2 md0 to md3 p40 to p43 (low-order 4 bits) p50 to p53 (high-order 4 bits) v dd pin name function voltage applecation pin for program memory write/verify (normally v dd potential). address update clock input for program memory write/verify. inverse of x1 pin signal is input to x2 pin. operating mode selection pin for program memory write/verify. 8-bit data input/output pin for progrm memory write/verify. supply voltage application pin. applies 2.7 to 6.0 v in normal operation, and 6 v for program memory write/verify. note 1. pins not used in a program memory write/verify operation are handled as follows: ports 0 to 2, ports 6 to 15 t0 to t9, an0 to an3, xt1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? connect to gnd v load , av ref , av ss , reset av dd ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? connect to v dd xt2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? leave open 2. on the m pd75p238kf which is equipped with an erase window the shading cover film should be attached except when performing eprom erasure. 3. since the m pd75p238gj one-time prom version is not provided with an erase window, program memory contents cannot be erased.
19 m pd75p238 operating mode setting operating mode v pp v dd md0 md1 md2 md3 + 12.5 v + 6 v h l h l l h h h write mode l l h h verify mode h h h program inhibit mode program memory address zero-clear remarks : l or h 5.1 program memory write/verify operating modes when +6 v is applied to the v dd pin and +12.5 v to the v pp pin, the m pd75p238 enters the program memory write/ verify mode. this mode comprises one of the operating modes shown in table 5-2 according to the setting of pins md0 to md3. table 5-2 program memory write/verify operating modes
20 m pd75p238 5.2 program memory write procedure the procedure for writing to program memory is as shown below, allowing high-speed writing. (1) unused pins are connected to v ss . the x1 pin is driven low. (2) 5 v is supplied to the v dd and v pp pins. (3) 10 m s wait. (4) program memory address zero-clear mode. (5) 6v is supplied to v dd , 12.5 v to v pp . (6) program inhibit mode. (7) data is written in 1 ms write mode. (8) program inhibit mode. (9) verify mode. if write is successful go to (10), otherwise repeat (7) to (9). (10) (number of times written in (7) to (9): x) 1 ms additional writes. (11) program inhibit mode. (12) program memory address is updated (+1) by inputting 4 pulses to the x1 pin. (13) steps (7) to (12) are repeated until the last address. (14) program memory address zero-clear mode. (15) v dd / v pp pin voltage is changed to 5 v. (16) power-off. steps (2) to (12) of this procedure are shown in fig. 5-1. fig. 5-1 program memory write timing v pp v dd v dd p40 to p43 0 to p53 md0 (p30) x1 md3 (p33) md2 (p32) md1 (p31) ? ? ? ? v dd + 1 v dd v pp data input data input write verify additional write address increment repeated x times data output ? ? ? ?
21 m pd75p238 v pp v dd 5.3 program memory read procedure m pd75p238 program memory contents can be read using the following procedure. reading is performed in verify mode. (1) unused pins are connected to v ss . the x1 pin is driven low. (2) 5 v is supplied to the v dd and v pp pins. (3) 10 m s wait. (4) program memory address zero-clear mode. (5) 6 v supplied to v dd , and 12.5 v to v pp . (6) program inhibit mode. (7) verify mode. when clock pulses are input to the x1 pin, data is output sequentially, one address per 4-pulse-input cycle. (8) program inhibit mode. (9) program memory address zero-clear mode. (10) v dd / v pp pin voltage is changed to 5 v. (11) power-off. steps (2) to (9) of this procedure are shown in fig. 5-2. x1 p40 to p43 p50 to p53 md0 (p30) md1 (p31) md2 (p32) md3 (p33) ? ? ? ? ? fig. 5-2 program memory read timing ? ? ?? v dd v dd +1 v dd v pp data output data output "l"
22 m pd75p238 5.4 erasure ( m pd75p238kf only) the programmed data contents of the m pd75p238kf can be erased by exposure to ultraviolet light through the window in the top. the ultraviolet wave length which effects erasure is 250 nm, and the quantity of radiation necesary for complete erasure is 15 w?s/ cm 2 (ultraviolet radiation intensity x erasure time). using a commercially available ultraviolet lamp (254 nm vavelength, 12 mw/cm 2 intensity) erasure can be accomplished in approximately 15 to 20 minutes. note 1. memory contents may also be erased by prolonged exposure to direct sunlight fluorescent lighting. to protect the contents ensure that the top window is masked with the shading cover film. the shading cover film supplied with nec's uv eprom products should be used. 2. when carrying out erasure the distance between the ultraviolet lamp and the m pd75p238kf should normally be no greater than 2.5 cm. remarks a longer erasure time may be required if there is deterioration of the ultraviolet lamp, or if the package window is not clean, etc.
23 m pd75p238 6. electrical specifications absolute maximum ratings (ta = 25 c) parameter symbol test conditions rating unit v dd C0.3 to +7.0 v supply voltage v load v dd C40 to v dd +0.3 v v pp C0.3 to +13.5 v v i1 except ports 4, 5 C0.3 to v dd +0.3 v input voltage v i2 ports 4, 5 open-drain C0.3 to +11 v v o pins except display output pins C0.3 to v dd +0.3 v output voltage v od display output pins v dd C40 to v dd +0.3 v 1 pin except display output pins C15 ma s0 to s9, s16 to s23 1 pin C15 ma output current i oh high t0 to t15 1 pin C30 ma all pins except display output pins C30 ma all display output pins C120 ma peak value 30 ma 1 pin effective value 15 ma peak value 100 ma output current i ol * total of port 0, 2, 3, 4 low effective value 60 ma peak value 100 ma total of port 5 to 8 effective value 60 ma operating t opt C40 to +70 c temperature storage t stg C65 to +150 c temperature * the effective value should be calculated as follows. [effective value] = [peak value] duty note product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, or even momentarily. in other words, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute ratings are not exceeded. h
24 m pd75p238 *1. except the system clock oscillator, display controller and timer/pulse generator. 2. the operating power supply voltage range varies depending on the cycle time. refer to the section describing ac characteristics. operating supply voltage range (ta = C40 to +70 c) parameter test conditions min. max. unit cpu *1 *2 6.0 v display controller 4.5 6.0 v timer/pulse generator 4.5 6.0 v other hardware *1 2.7 6.0 v
25 m pd75p238 main system clock resonator characteristics (ta = C40 to +70 c, v dd = 2.7 to 6.0 v) recommended test resonator parameter min. typ. max. unit characteristics conditions oscillator 2.0 6.2 mhz frequency (f x ) *1 after v dd oscillation has reached stabilization min. value of 4ms time *2 oscillator voltage range. oscillator 2.0 4.19 6.2 mhz frequency (f x ) *1 v dd = 4.5 10 ms oscillation to 6.0 v stabilization time *2 30 ms x1 input 2.0 6.2 mhz frequency (f x ) *1 x1 input high and low level 81 250 ns width (t xh , t xl ) *1. oscillator frequency and input frequency indicate oscillator characteristics only. refer to the ac character- istics for the instruction execution time. 2. oscillation stability time is time required for oscillation to stabilize after v dd has reached the min. value in oscillation voltage range or stop mode has been released. note when the main system clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. ? the wiring should be kept as short as possible. ? no other signal lines should be crossed. ? keep away from lines caring a high fluctuating current. ? the oscillator capacitor grounding point should always be at the same potential as v ss . do not connect to a ground pattern carrying a high current. ? a signal should not be taken from the oscillator. ceramic resonator crystal resonator external clock v dd = oscillator voltage range h x1 x2 c2 c1 x1 x2 c2 c1 x1 x2 m pd74hcu04
26 m pd75p238 subsystem clock oscillator characteristics (ta = C40 to +70 c, v dd = 2.7 to 6.0 v) recommended test resonator parameter min. typ. max. unit characteristics conditions oscillator 32 32.768 35 khz frequency (f xt ) *1 v dd = 4.5 1.0 2 s to 6.0 v 10 s xt1 input 32 100 khz frequency (f xt ) *1 *1. oscillator frequency and input frequency indicate oscillator characteristics only. refer to the ac character- istics for the instruction execution time. 2. oscillation stability time is time required for oscillation to stabilize after v dd has reached the min. value in oscillation voltage range. note when subsystem clock oscillator is used, the following should be noted concerning wiring in the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc. ? the wiring should be kept as short as possible. ? no other signal lines should be crossed. ? keep away from lines caring a high fluctuating current. ? the oscillator capacitor grounding point should always be at the same potential as v ss . do not connect to a ground pattern carrying a high current. ? a signal should not be taken from the oscillator. the subsystem clock oscillator is a low-amplitude circuit in order to achieve a low consumption current, and is more prone to misoperation due to noise than the main system, clock oscillator. particular care is therefore required with the wiring method when the subsystem clock is used. xt1 xt2 x1 input high and low level 5 15 m s width (t xth , t xtl ) oscillation stabilization time *1 external clock crystal resonator capacitance (ta =25 c, v dd = 0 v) parameter symbol test conditions min. typ. max. unit input capacitance c i 15 pf output capacitance c o 15 pf (output except display output) input/output capacitance c io 15 pf output capacitance c o 35 pf (display output) xt1 xt2 c4 c3 r f = 1 mhz 0 v for pins except measured pins h
27 m pd75p238 recommended oscillator contants mainsystemclock : ceramic resonator (ta = C 40 to + 85 c) c2 30 C 30 C 30 C 30 C 30 C 30 C min. 2.7 3.0 3.3 4.0 max. 6.0 6.0 6.0 6.0 c1 30 C 30 C 30 C 30 C 30 C 30 C frequency (mhz) -------------------------- -------------------------- -------------------------- -------------------------- -------------------------- -------------------------- remarks on-chip capacitor product on-chip capacitor product on-chip capacitor product on-chip capacitor product on-chip capacitor product on-chip capacitor product --------------------------------------- --------------------------------------- --------------------------------------- --------------------------------------- --------------------------------------- --------------------------------------- main system clock : crystal resonator (ta = C 20 to + 70 c) c2 22 min. 4.0 max. 6.0 c1 22 hc-49/u-s recommended oscillator constants(pf) oscillator voltage range(v) 3.072 to 6.000 2.0 2.5 4.19 2.5 4.19 6.00 product name frequency (mhz) remarks recommended oscillator constants(pf) oscillator voltage range(v) csa2.0mg cst2.0mg csa2.5mg093 cst2.5mgw093 csa4.19mgu cst4.19mgwu csa2.5mg cst2.5mgw csa4.19mg cst4.19mgw csa6.0mg cst6.0mgw product name murata mfg. maunfac- turer kinseki, ltd. maunfac- turer ---------------------------- ---------------------------- ---------------------------- ---------------------------- ---------------------------- ----------------------------
28 m pd75p238 v dd = 4.5 to 6.0 v 0.7 v dd v dd v input voltage high input voltage low output voltage low output voltage high v ih1 v ih4 v il1 v oh v ol input leakage current high i lih1 i lil1 input leakage current low sb0, sb1 all output pins ports 3, 4, 5 dc characteristics (ta = C40 to +70 c, v dd = 2.7 to 6.0 v) (1/3) parameter symbol test conditions min. typ. max. unit all ports and pins except those listed below. v ih2 port 0, 1, reset, p81, p83 0.8 v dd v dd v v ih3 x1, x2, xt1 v dd C0.4 v dd v 0.65 v dd v dd v 0.7 v dd v dd v v ih5 port 4, 5 open-drain 0.7 v dd 10 v all ports and pins except those listed below. v il2 port 0, 1, reset, p81, p83 0 0.2 v dd v v il3 x1, x2, xt1 0 0.4 v v dd = 4.5 to 6.0 v v dd = 2.7 i oh = v dd C0.5 v to 6.0 v C100 m a v dd = 4.5 to 6.0 v v dd = 4.5 i ol = 0.4 v to 6.0 v 1.6 ma v dd = 2.7 i ol = 0.5 v to 6.0 v 400 m a open-drain 0.2 v dd v pull-up resistor 3 1 k w all ports and pins except those listed below. i lih2 x1, x2, xt1 20 m a i lih3 ports 4, 5 v in = 10 v 20 m a all ports and pins except those listed below. i lil2 x1, x2, xt1 C20 m a all output pins, except port 4, 5 and p03 C3 m a 3 m a v in = 0 v v in = v dd i oh = C1 ma v dd C1.0 v i oh = 15 ma 0.4 2.0 v port 7 0 0.3 v dd v
29 m pd75p238 dc characteristics (ta = C40 to +70 c, v dd = 2.7 to 6.0 v) (2/3) output leakage current high output leakage current low display output current on-chip pull-up resistor power supply current *1 v out = v dd 3 m a v dd = 4.5 to 6.0 v v od = v dd C 2 v display output operat- ing mode halt mode operat- ing mode halt mode i loh1 i lol2 i od i lol1 r l r v1 i ddi i dd2 i ddi i dd2 parameter symbol test conditions min. typ. max. unit all ports and pins except those listed below. i loh2 port 4, 5 v out = 10 v 20 m a all ports and pins except those listed below. display v out = v load = C10 m a output v dd C 35 v s0 to s9, C3 C5.5 ma s16 to s23 t0 to t15 C15 C22 ma on-chip pull-down resistor v od C v load = 35 v 25 50 135 k w (mask option) port 0, 1, 2, 3, v dd = 5 v 10% 15 40 80 k w 6 (except p00) v in = 0 v v dd = 3 v 10% 30 300 k w v dd = 5v 918ma 10% *2 v dd = 3 v 13ma 10% *3 v dd = 5 v 900 2700 m a 10% v dd = 3 v 300 900 m a 10% v dd = 5 v 515ma 10% *2 v dd = 3 v 0.9 2.7 ma 10% *3 v dd = 5 v 600 1800 m a 10% v dd = 3 v 200 600 m a 10% *1. current to the on-chip pull-down resistor (pull-up) and power-on reset circuit (mask option) is not included. 2. when the processor clock control register (pcc) is set to 0011 and is operated at high-speed mode. 3. when the pcc register is set to 0000 and is operated in the low-speed mode. 4. includes the case where the subsystem clock oscillating. v out = 0 v C3 m a 6mhz crystal oscillation c1 = c2 = 22 pf *4 4.19mhz crystal oscillation c1 = c2 = 22 pf *4
30 m pd75p238 operat- i dd3 ing 100 300 m a mode halt v dd = 3 v 20 60 m a mode 10% v dd = 5 v 10% 0.5 20 m a i dd5 0.3 10 m a ta = 25 c5 m a 32 khz crystal 5 15 m a oscillation *2 dc characteristics (ta = C40 to +70 c, v dd = 2.7 to 6.0 v) (3/3) parameter symbol test conditions min. typ. max. unit power supply current *1 i dd4 i dd6 32 khz crystal oscillation *2 stop mode v dd = 3 v 10% v dd = 3 v 10% v dd = 3 v 10% xt1 = 0 v stop mode *1. current to the on-chip pull-down resistor (pull-up) and power-on reset circuit (mask option) is not included. 2. when the system clock control register (scc) is set to 1001 and is operated with the subsystem clock with main system clock oscillation stopped. *1. absolute accuracy except quantization error ( 1/2 lsb). 2. time from execution of conversion start instruction to eoc = 1 (28.0 m s when f x = 6.0 mhz, 40.1 m s when f x = 4.19 mhz) 3. time from execution of conversion start instruction to the end of sampling (7.33 m s when f x = 6.0 mhz, 10.5 m s when f x = 4.19 mhz) resolution 888bit C10 ta +70 c 1.5 lsb C40 ta < C10 c 2.0 conversion time t conv *2 168/f x m s sampling time t samp *3 44/f x m s analog input voltage analog input impedance av ref current i aref 1.0 2.0 ma a/d converter characteristics (ta = C40 to +70 c, v dd = 2.7 to 6.0 v, av ss = v ss = 0 v, 2.7 av dd v dd ) parameter symbol test conditions min. typ. max. unit absolute accuracy *1 v ian av ss av ref v r an 1000 m w 2.5 v av ref v dd
31 m pd75p238 *1. cpu clock ( f ) cycle time is determined by the oscillator for frequency of the connected oscil- lator, the system clock control register (scc) and processor clock control register (pcc). the cycle time t cy characteristics for supply voltage v dd when the main system clock is in operation is shown on the right. 2. 2t cy or 128/f x is set by interrupt mode register (im0) setting. ac characteristics (ta = C40 to +70 c, v dd = 2.7 to 6.0 v) (1) basic operation parameter symbol test conditions min. typ. max. unit operation with v dd = 4.75 0.67 64 m s main system to 6.0 v clock 2.6 64 m s operation with subsystem clock 114 122 125 m s v dd = 4.5 to 6.0 v 0 1 mhz 0 275 khz v dd = 4.5 to 6.0 v 0.48 m s 1.8 m s interrupt input high int0 *2 m s and low-level widths int1, 2, 4 10 m s reset low level 10 m s widths t cy f ti t tih , t til t rsl t inth , t intl ti0 input high and low-level widths t cy vs v dd (when main system clock is in operation) cycle time t cy [ s] power supply voltage v dd [v] 0 1 2 3 4 5 6 0.5 1 2 3 4 5 60 64 70 6 operation guaranteed range m ti0 input frequency cpu clock cycle time (minimum instruction execution time = one machine cycle) *1
32 m pd75p238 (2) serial transfer operation (a) 2-wired and 3-wired serial i/o modes (sck ... internal clock output) parameter symbol test conditions min. typ. max. unit f x = 6.0 mhz 1340 ns f x = 4.19 mhz 1600 ns f x = 6.0 mhz 2680 ns f x = 4.19 mhz 3800 ns (t kcy1 /2) ns -50 (t kcy1 /2) ns -150 150 ns si hold time 400 ns (from sck - ) v dd = 4.5 250 ns r l = 1 k w , to 6.0 v c l = 100 pf * 1000 ns * r l and c l denote load resistor and load capacitance of so output line. (b) 2-wired and 3-wired serial i/o modes (sck ... external clock input) parameter symbol test conditions min. typ. max. unit v dd = 4.5 to 6.0 v 800 ns 3200 ns v dd = 4.5 to 6.0 v 400 ns 1600 ns 100 ns 400 ns 300 ns 1000 ns * r l and c l denote load resistor and load capacitance of so output line. sck cycle time t kcy1 v dd = 4.5 to 6.0 v v dd = 4.5 to 6.0 v sck high and low t kl1 level widths t kh1 t sik1 t ksi1 t kso1 so output delay time from sck sck cycle time t kcy2 sck high and low t kl2 level widths t kh2 t sik2 t ksi2 t kso2 so output delay time from sck si setup time (to sck - ) si setup time (to sck - ) si hold time (from sck - ) r l = 1 k w , c l = 100 pf * v dd = 4.5 to 6.0 v
33 m pd75p238 (c) sbi mode (sck ... internal clock output (master)) parameter symbol test conditions min. typ. max. unit f x = 6.0 mhz 1340 ns f x = 4.19 mhz 1600 ns f x = 6.0 mhz 2680 ns f x = 4.19 mhz 3800 ns v dd = 4.5 to 6.0 v t kcy3 /2-50 ns t kcy3 /2-150 ns sb0, 1 setup time 150 ns (to sck - ) sb0, 1 hold time (from sck - ) sb0, 1 output r l = 1 k w ,v dd = 4.5 to 6.0 v 0 250 ns delay time from c l = 100 pf * sck 0 1000 ns sb0, 1 from sck - sck from sb0, 1 t sbk t kcy3 ns sb0, 1 low level widths sb0, 1 high level widths * r l and c l denote load resistor and load capacitance of so output lines. v dd = 4.5 to 6.0 v sck cycle time t kcy3 sck high and low level widths t kl3 t kh3 t sik3 t ksi3 t kso3 t ksb t kcy3 ns t kcy3 /2 ns t sbl t kcy3 ns t sbh t kcy3 ns
34 m pd75p238 (d) sbi mode (sck ... external clock input (slave)) parameter symbol test conditions min. typ. max. unit sck cycle time t kcy4 v dd = 4.5 to 6.0 v 800 ns 3200 ns sck high and low t kl4 v dd = 4.5 to 6.0 v 400 ns level widths t kh4 1600 ns sb0, 1 setup time (to sck - ) sb0, 1 hold time (from sck - ) sb0, 1 output v dd = 4.5 to 6.0 v 0 300 ns delay time from sck 0 1000 ns sb0, 1 from sck - t ksb t kcy4 ns sck from sb0, 1 t sbk t kcy4 ns sb0, 1 low level widths sb0, 1 high level widths * r l and c l denote load resistor and load capacitance of so output lines. t ksi4 t kcy4/ 2ns t sik4 100 ns t sbl t kcy4 ns t sbh t kcy4 ns t kso4 r l = 1 k w c l = 100 pf *
35 m pd75p238 ac timing test points (except x1 and xt1 inputs) clock timings ti0 timing 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd test points x1 input 1/f x t xl t xh v dd -0.5 v 0.4 v xt1 input 1/f xt t xtl t xth v dd -0.5 v 0.4 v ti0 1/f ti t til t tih
36 m pd75p238 serial transfer timing 3-wired serial i/o mode: 2-wired serial i/o mode: sck t kcy1 t kh1 t kl1 input data output data t sik1 t ksi1 t kso1 si so t kso2 t kl2 t kh2 t kcy2 sck sb0,1 t sik2 t ksi2
37 m pd75p238 serial transfer timing bus release signal transfer: command signal transfer: interrupt input timing reset input timing t ksb t sbl t sbh t sbk t kso3,4 t sik3,4 t ksi3,4 t kl3,4 t kh3,4 t kcy3,4 sck sb0,1 t ksb t kso3,4 t sik3,4 t ksi3,4 t kl3,4 t kh3,4 t kcy3,4 sck sb0,1 t sbk t intl t inth int0,1,2,4 t rsl reset
38 m pd75p238 v dddr 2.0 6.0 v i dddr v dddr = 2.0 v 0.1 10 m a data memory stop mode low supply voltage data retention characteristics (ta = C40 to 70 c) parameter symbol test conditions min. typ. max. unit data retention power supply voltage data retention power supply current *1 release signal set time oscillation release by reset 2 17 /fx ms stabilization wait time *2 release by interrupt request *3 ms *1. current to the on-chip pull-up resistor and power-on reset circuit (mask option) is not included. 2. oscillation stability wait time is time to stop cpu operation to prevent unstable operation upon oscillation start. 3. according to the setting of the basic interval timer mode register (btm). (see below) wait time btm3 btm2 btm1 btm0 values at f x = 6.0 mhz in parentheses values at f x = 4.19 mhz in parentheses 0 0 0 2 20 /fx (approx. 175 ms) 2 20 /fx (approx. 250 ms) 0 1 1 2 17 /fx (approx. 21.8 ms) 2 17 /fx (approx. 31.3 ms) 1 0 1 2 15 /fx (approx. 5.46 ms) 2 15 /fx (approx. 7.82 ms) 1 1 1 2 13 /fx (approx. 1.37 ms) 2 13 /fx (approx. 1.95 ms) t srel 0 m s t wait
39 m pd75p238 data retention timing (standby release signal: stop mode release by interrupt signal) data retention timing (stop mode release by reset) stop mode data retention mode stop instruction execution reset v dd internal reset operation halt mode operating mode v dddr t srel t wait stop mode data retention mode stop instruction execution v dd halt mode operating mode v dddr t srel t wait standby release signal (interrupt request)
40 m pd75p238 dc programming characteristics (ta = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) parameter symbol test conditions min. typ. max. unit v ih1 except x1 and x2 0.7 v dd v dd v v ih2 x1, x2 v dd C0.5 v dd v v il1 except x1 and x2 0 0.3 v dd v v il2 x1, x2 0 0.4 v input leakage current output voltage high output voltage low v dd supply current i dd 30 ma v pp supply current i pp md0 = v il , mdi =v ih 30 ma note 1. v pp , including overshoot, should not exceed +13.5 v. 2. v dd should be applied before v pp and cut after v pp . ac programming characteristics (ta = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) (1/2) parameter symbol *1 test conditions min. typ. max. unit address setup time *2 (to md0 ) md1 setup time (to md0 )t m1s t oes 2 m s data setup time (to md0 )t ds t ds 2 m s address hold time *2 (from md0 - ) data hold time (from md0 - ) data output float delay time from md0 - v pp setup time (to md3 - )t vps t vps 2 m s v dd setup time (to md3 - )t vds t vcs 2 m s initial program pulse widths t pw t pw 0.95 1.0 1.05 ms additional program pulse widths md0 setup time (to md1 - )t mos t ces 2 m s data output delay time from md0 *1. the corresponding m pd27c256 symbol. 2 . internal address signal is incremented by one on the rise of fourth x1 input and is not connected to the pin. input voltage high input voltage low i li v in = v il or v ih 10 m a v oh i oh = C1 ma v dd C1.0 v v ol i oh = 1.6 ma 0.4 v t ah t ah 2 m s t as t as 2 m s t dh t dh 2 m s t df t df 0 130 ns t opw t opw 0.95 21.0 ms t dv t dv md0 = md1 = v il 1 m s
41 m pd75p238 ac programming characteristics (ta = 25 5 c, v dd = 6.0 0.25 v, v pp = 12.5 0.3 v, v ss = 0 v) (2/2) parameter symbol *1 test conditions min. typ. max. unit md1 hold time 2 m s (from md0 - ) t m1h + t m1r 3 50 m s md1 recovered time 2 m s (to md0 ) program counter reset time t pcr 10 m s x1 input high and low level widths x1 input frequency f x 4.19 mhz initial mode set time t i 2 m s md3 setup time (to md1 - )t m3s 2 m s md3 hold time (from md1 ) md3 setup time (to md0 )t m3sr when reading program memory 2 m s data output delay time from address *2 data output hold time from address *2 md3 hold time (from md0 - ) data output float delay time from md3 *1. the corresponding m pd27c256 symbol. 2 . internal address signal is incremented by one on the rise of fourth x1 input and is not connected to the pin. t m1h t oeh t m1r t or t xh , t xl 0.125 m s t m3h 2 m s t had t oh when reading program memory 0 130 ns t dad t acc when reading program memory 2 m s t m3hr when reading program memory 2 m s t dfr when reading program memory 2 m s
42 m pd75p238 read timing of program memory write timing of program memory p40 to p43 p50 to p53 v pp v dd v pp v dd v dd + 1 v dd x1 md0 md1 md2 md3 t vps t vds t xh t xl t dad t had output data output data t dv t i t pcr t m3sr t m3hr t dfr t vps t vds v dd v pp v dd v dd + 1 v pp v dd x1 p40 to p43 p50 to p53 input data output data input data input data t xh t xl t as t ah t ds t opw t mos t m1r t pw t m1h t m1s t pcr t m3s t m3h md0 md1 md2 md3 t i t ds t oh t dv t df t dh
43 m pd75p238 7. package information n a m f 1 b 71 72 47 k l 94 pin plastic qfp ( 20) 94 24 23 48 p g 1 d c detail of lead end s q 55? f 2 1 g 2 m i h j s94gj-80-5bg-2 item millimeters inches a b c d f 1 f 2 g 1 g 2 h i j 23.2 0.4 20.0 0.2 0.8 1.6 0.8 20.0 0.2 0.913 0.063 0.031 0.031 0.014 0.787 note k l 0.8 0.2 1.6 0.2 0.15 0.35 0.10 0.031 0.063 0.008 each lead centerline is located within 0.15 mm (0.006 inch) of its true position (t.p.) at maximum material condition. 0.006 0.063 0.787 0.8 (t.p.) 0.031 (t.p.) m 0.15 0.006 0.913 23.2 0.4 1.6 n 0.12 0.005 p 3.7 0.146 +0.009 ?.008 +0.009 ?.008 q 0.1 0.1 0.004 0.004 s 4.0 max. 0.158 max. +0.10 ?.05 +0.017 ?.016 +0.017 ?.016 +0.004 ?.005 +0.004 ?.003 +0.009 ?.008
44 m pd75p238 x94kw-80a-1 item millimeters inches note each lead centerline is located within 0.08 mm (0.003 inch) of its true position (t.p.) at maximum material condition. a b c d e f g h i j k q r s t u w 20.0 ? 0.4 18.0 18.0 20.0 ? 0.4 1.94 2.14 4.064 max. 0.51 ? 0.10 0.08 0.8 (t.p.) 1.0 ? 0.2 c 1.0 1.6 1.6 r 1.75 11.5 0.75 ? 0.2 0.787 0.709 0.709 0.787 0.076 0.084 0.160 max. 0.020 ? 0.004 0.003 0.031 (t.p.) 0.039 c 0.039 0.063 0.063 0.069 0.453 0.030 +0.017 ? 0.016 +0.009 ? 0.008 +0.008 ? 0.009 94 pin ceramic wqfn a b d c t q u e i m h j r s 94 1 k y w +0.017 ? 0.016 f g
45 m pd75p238 8. recommended soldering conditions this product should be soldered and mounted under the conditions recommended in the table below. for details of recommended soldering conditions, refer to the information document "surface mount technol- ogy manual" (iei-1207) . for soldering methods and conditions other than those recommended below, contact our salesman. table 8-1 surface mount type soldering conditions m pd75p238gj- -5bg : 94-pin plastic qfp ( n n 20 mm) h infrared reflow vps pin part heating soldering method soldering conditions ir30-107-1 vp15-107-1 recommended condition symbol package peak temperature: 230 c, duration: 30 sec. max. (at 210 c or above); number of times: once, time limit: 7 days * (125 c prebaking requires 10 hours thereafter) package peak temperature: 215 c, duration: 40 sec. max. (at 200 c or above); number of times: once, time limit: 7 days * (125 c prebaking requires 10 hours thereafter) pin part temperature: 300 c max.; duration: 3 sec. max., (per device side) * for the storage period after dry-pack decapsulation, storage conditions are max. 25 c, 65% rh. note use of more than one soldering method should be avoided (except in the case of pin part heating).
46 m pd75p238 appendix a. development tools the following support tools are available for system development using the m pd75p238. ie-75000-r *1 ie-75001-r ie-75000-r-em *2 ep-75238gj-r ev-9200g-94 pg-1500 pa-75p238gj pa-75p238kf ie control program pg-1500 controller ra75x relocatable assembler softwar hardware ie-75000-r/ie-75001-r emulation board m pd75p238 emulation probe 94-pin conversion socket ev-9200g-94 is provided prom programmer pg-1500 connected with m pd75p238gj prom program adapter pg-1500 connected with m pd75p238kf prom program adapter 75x series in-circuit emulator host machine pc-9800 series (ms-dos? ver.3.30 to ver.5.00a *3 ) ibm pc/at? (pc dos? ver.3.1) *1. maintenance product 2. not incorporated in ie-75001-r 3. the task swap function, which is provided with ver.5.00/5.00a. is not available with this software. remarks for development tools manufactured by a third party, see the "75x series selection guide" (if-151) .
47 m pd75p238 appendix b. related documents device related documents document name document no. users manual instruction application table 75x series selection guide development tools related documents document name document no. ie-75000-r/ie-75001-r users manual ie-75000-r-em users manual ep-75238gj-r users manual pg-1500 users manual ra75x assembler package users manual operation volume language volume pg-1500 controller users manual other documents document name document no. package manual surface mount technology manual quality grade on nec semiconductor devices nec semiconductor device reliability & quality control electrostatic discharge (esd) test semiconductor devices quality guarantee guide microcomputer related products guide other manufactures volume note the contents of the above related documents are subjected to change without notice. the latest documents should be used for design, etc. hardware software h
48 m pd75p238
49 m pd75p238
m pd75p238 [memo] fip is a trademark of nec corporation. ms-dos is a trademark of microsoft corporation. pc dos, pc/at are trademarks of ibm corporation. m4 92.6 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. the devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. if customers intend to use nec devices for above applications or they intend to use "standard" quality grade nec devices for applications not intended by nec, please contact our sales people in advance. application examples recommended by nec corporation standard : computer, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots, audio and visual equipment, other consumer products, etc. special : automotive and transportation equipment, traffic control systems, antidisaster systems, anticrime systems, etc.

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